Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design
نویسندگان
چکیده
To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. overcome roadblocks logic cell design using this emerging technology, work explores compact modeling 3D GAA-JLNTs based on physics transport. The model features an explicit continuous analytical form drain current calculations adapted for a 14 channel technology and has been validated against extensive characterization results wide range JLNT geometry, depicting good accuracy. Finally, preliminary simulations have explored performance assessment circuits, such as inverters with passive load, active load complementary topologies well ring oscillators, designed developed model.
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ژورنال
عنوان ژورنال: Solid-state Electronics
سال: 2021
ISSN: ['0038-1101', '1879-2405']
DOI: https://doi.org/10.1016/j.sse.2021.108125